(A) Field of the Invention
The present invention is related to a clock multiplier, more specifically, to a clock multiplier capable of modulating the duty cycle of the output clock.
(B) Description of Related Art
With the rising demand of higher clock frequency to semiconductor devices, on-chip clock multipliers are widely used nowadays. Conventionally, the relatively expensive phase-lock loops (PLLs) and lower-cost clock doublers are chosen as multiplication solutions.
FIG. 1 illustrates a function block diagram of a clock multiplier 10 using PLL technique, which consists of a divided-by-M counter 11, a phase-frequency detector 12, a charge pump 13, a loop filter 14, a voltage-controlled oscillator (VCO) 15 and a divided-by-N counter 16. In accordance with such design, the frequency of the output clock (CLKOUT) is equivalent to that of the input clock (CLKIN) multiplied by N/M. Because of the high circuit complexity, the cost of silicon processing and testing overhead typically preclude the use of such PLLs in cost-sensitive integrated circuits.
FIG. 2 illustrates the circuitry and the timings of a known clock doubler 20. The clock doubler 20 consists of a delay line 22 and an exclusive OR (XOR) gate 24. If the period of a CLKIN is T, the delay line 22 will generate a delayed-clock (CLKDLY) delaying T/4. Accordingly, the CLKIN and the CLKDLY are inputted to the XOR gate 24 to generate a CLKOUT with double frequency. Although the clock doubler is much simpler and cheaper, it still suffers from two limitations. First, the useful frequency range is limited as a fixed delay line is used. Thus, if the applied frequency is changed, the delay line has to be changed as well. Secondly, the delay line is a circuit constituted by resistor-capacitor (RC) components, which are easily affected by process, temperature, supply voltage and clock frequency change, so the duty cycle of the delay line will be changed.
Nowadays, clock multipliers are widely applied in various digital integrated circuits. However, current clock multipliers are either more costly or ineligible, and thus it is necessary to develop a low-cost clock multiplier capable of adjusting the duty cycle of the output clock.